Current Steering Dac Thesis

Thus, the number of transistors in the digital part of DAC is reduced and higher sampling rate is obtained.Furthermore, the proposed current mode decoder has lower output voltage variation and consequently lower dynamic power dissipation.

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It is seen that at high frequency the spectral performance of DAC degrades rapidly due to the increase in parasitics.

Our aim in this work is to improve static as well dynamic performance by optimum design of current sources.

The glitch is short span high magnitude output mostly occur due to mid-code transition.

In unary architecture requirement of physical area on chip is more, as well as it has high power dissipation, but has advantage of good differential nonlinearity (DNL).

In conventional segmented CS architecture, the MSB is implemented in unary and LSB is implemented in binary.

In the proposed design the binary section of segmented architecture is replaced by Chinese abacus sub-DAC to minimize noise i.e., glitch energy and to improve the spurious performance.

The maximum spurious free dynamic rage (SFDR) achieved is 65.02 d B.

This present study describes the designing of current steering DAC, which is an important block in many VLSI chips.

The technology used for design is UMC 180 nm CMOS process with six metal layers.

The proposed 10-bit DAC achieves maximum DNL and integral nonlinearity (INL) of 0.28 LSB and 0.19 LSB, respectively.


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